The invention relates to a semiconductor memory cell comprising an electrically floating gate which is rechargeable with the aid of a charge injector and extends throughout the channel region of a memory transistor whose source-drain region is connected in series with the source-drain region of a selection transistor between a first bit line and a second bit line of a memory matrix.
Such types of memory cells are known, for example, from the technical journal "Electronics" of Feb. 10, 1982, pp. 121 and 122, and from the technical journal "IBM Technical Disclosure Bulletin" 23/2 (July 1980) pp. 661 to 663.
A serious manufacturing yield problem occurs in the manufacture of memory (storage) matrices comprising memory (storage) cells which contain electrically reprogrammable insulated-gate field-effect memory transistors because only memory matrices can be used having memory cells which are all unobjectionable.
International patent application No. WO 83/02847 shows one attempt to solve this problem by providing redundant columns which, upon detection of one or more faulty cells in a column, are switched instead of the defective column by employing a programmable redundancy decoder.
In European Pat. No. 0,098,079 an electrically programmable redundancy decoder is used which, in accordance with its programming, replaces a defective memory cell, upon selection, with an unobjectionable memory cell.
Such measures for solving the aforementioned problem, however, involve an additional peripheral circuit investment, and also require a measuring of the memory matrix and a programming of the circuit means for effecting the replacement of a defective cell by a redundant faultless cell.
For the purpose of overcoming these disadvantages, the invention proceeds from the idea of providing a memory cell having an "internal" redundancy, that is, a memory cell which is capable of maintaining its storage property upon occurrence of a fault in the insulating layer surrounding the storage medium, in particular of a fault of the injector oxide between the semiconductor substrate and the floating gate, without requiring the investment of a peripheral redundancy decoder and the re-addressing for replacing a faulty memory cell by an unobjectionable redundant cell. Such a memory cell would not only increase the yield in functionable memory matrices, but would also improve the endurance, because then there is also maintained the storage capacity of the cell when local defects in the cell occur in the course of the operating time.